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M34116
PCM CONFERENCE CALL AND TONE GENERATION CIRCUIT
PRELIMINARY DATA
HW AND SW COMPATIBLE WITH M116 1 TO 64 SERIAL CHANNELS PER FRAME (CONTROLLED BY SYNC SIGNAL PERIOD) 29 MAXIMUM CONFERENCES 1 TO 64 SERIAL CHANNELS PER CONFERENCES 3 SIMULTANEOUS OPERATION MODES AVAILABLE: CONFERENCE, TRANSPARENT AND TONE GENERATION TYPICAL BIT RATES: 1536/1544/2048/4096Kbits/s COMPATIBLE WITH ALL KINDS OF PCM FORMAT AND A LAW (PIN PROGRAMMABLE) EQUAL PRIORITY TO EVERY CHANNEL ONE FRAME AND ONE CHANNEL DELAY FROM SENDING TO RECEIVING OVERFLOW INFORMATION FOR EACH CONFERENCE BY PIN OS (OVERFLOW SIGNALLING) AND ON DATA BUS ON MPU REQUEST INSTRUCTION SET COMPATIBLE WITH M3488 PROGRAMMABLE INPUT AND OUTPUT ATTENUATION OR GAIN FROM 0 TO 15dB WITH STEP OF 1dB FOR EACH CHANNEL TONE GENERATION FROM 3.9Hz TO 3938Hz WITH MIN. STEP OF 3.9Hz TOTAL OF 7 DIFFERENT TONE OUTPUTS IN PARALLEL PROGRAMMABLE VIA MPU (MAXIMUM 4 DIFFERENT FREQUENCIES AND DURATIONS) 1 MELODY OF MAXIMUM 32 PROGRAMMABLE FREQUENCIES AND DURATIONS 5V POWER SUPPLY TTL COMPATIBLE INPUT LEVELS, CMOS/TTL COMPATIBLE OUTPUT LEVELS MAIN INSTRUCTIONS CONTROLLED BY MICROPROCESSOR INTERFACE: - Channel connection to a conference - Channel attenuation or gain - Channel disconnection from both conference and transparent modes - Tone and melody generation - Overflow status - Operating mode - Channel status
January 1995
DIP24 ORDERING NUMBER: M34116B1
PLCC28 ORDERING NUMBER: M34116C1
DESCRIPTION The M34116 is a product specifically designed for applications in PCM digital exchanges. It is able to handle up to 64 channels in any conferences combination from 1 to 29 conferences in parallel and to generate seven different tones and one melody. The parties in a conference must previously be allocated through the Digital Switching Matrix (M3488) in a single serial wire at M34116 PCM input (IN PCM pin). The M34116 is full pin and function compatible with the M116. In addition, it has the capability to generate tone directly coded in PCM. For the conference function, each channel is converted inside the chip from PCM law to linear law (14 bits). Then it is added to its conference, and the sample of the previous frame is subtracted from the conference. In this way a new conference sum signal is generated. The channel output signal will contain the information of all the other channels in its conference except its own. After the PCM encoding, the data is serialized by the M34116 in the same sequence as the PCM input frame, with one frame (plus one channel) delay and will be reallocated by the DSM (M3488) at the final channel and bus position. A programmable attenuation or gain can be set on each channel and for every function: conference, tone generation and transparent mode.
1/23
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
M34116
PIN CONNECTIONS (Top view)
DIP24
PLCC28
ABSOLUTE MAXIMUM RATINGS
Symbol VDD (*) Vi VO (off) Ptot Tstg Top Supply Voltage Input Voltage Off State Output Voltage Total Power Dissipation Storage Temperature Operating Temperature Parameter Value - 0.3 to 7 - 0.3 to VDD - 0.3 to 7 500 - 65 to 150 0 to 70 V mW C C Unit V
Stresses above those listed under "Absolute Maximum Ratings" may causes permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1: PCM Conference Call Insertion Scheme
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M34116
PIN DESCRIPTION
DIP No 1 PLCC No 2 Pin TD Function
2
3
4
5
6 to 13
14 15
16 17
18 19
20
21
22
23 24
M116 operating mode only. Tone Duration input pin. When TD = 1, a PCM coded tone (instead of PCM data) is sent out to all channels enabled by the IT bit. TD is latched by the SYNC signal so that all channels have the same tone during the same number of frames. TD = 0 for normal operation. 3 TF M116 operating mode only. Tone Frequency input pin. When TF = 1, the tone amplitude is high. When TF = 0, the tone amplitude is low. TF is latched by SYNC. The PCM coded tone level corresponds to 1/10 of the full scale. For M34116 operating mode: Melody waveform select input pin. When TF = 1, the PCM output of the melody represents a square wave. When TF = 0, it represents a sine wave. In both cases, the rms level is the same and is equal to - 6 dBm0 if no attenuation or gain is programmed. 4 RESET Master reset input pin. This pin is active low and must be used at the very beginning after power up to initialize the device or when switching from A law to Mu law. The Internal initialization routine takes 2 time frames starting from the rising edge of RESET. During this initialization time, all data bus and PCM output are pulled to a high impedance state. 5 OS Overflow Signalling output pin. When OS = 0 one conference is in overflow. This signal is anticipated over half time slot with respect to the output channel involved in the conference in overflow. Example: if output channel 4 is one of the parties of one conference in overflow, OS = 0 during the second half of the time slot corresponding to output channel 3 and during the first half of the time slot corresponding to output channel 4. 6 OUT PCM output pin. The bit rate is 4096Kbits/s max. The sign bit is the first bit of the serial PCM sequence. The first bit of the first channel is found at the rising edge of the CLOCK signal preceding the rising edge of the SYNC signal. The output buffer is open drain to allow for multiple connections. D0 to Bidirectional Data bus pins. Data and instructions are transferred to or from the 7, D7 microprocessor. D0 is the Least Significant Bit. The bus is tristate when RESET is low 9 to 11, and/or CS is high. 13 to 16 17 VDD +5V Supply input. 100nF decoupling capacitor recommended. 18 C/D Control Data input pin. In a write operation C/D = 0 qualifies any bus content as data while C/D = 1 qualifies it as an opcode. For M116 operating mode only: in a read operation, the overflow information of the first eight conferences is selected by C/D = 0, the overflow of the last two conferences and the status by C/D = 1. 19 CS Chip Select input pin. When CS = 0, data and instructions can be transferred to or from the external microprocessor and when CS = 1 the data bus is in tristate. 20 RD Read control input pin. When RD = 0, read operation is performed. When match conditions for the opcode exists, data is transferred to the external microprocessor on the falling edge of RD. 21 WR Write control input pin. Instructions and opcode from the external microprocessor are latched on the rising edge of WR. 23 SYNC Synchronization input pin. The rising edge of CLOCK preceding the rising edge of SYNC corresponds to the first bit of the first channel except for PCM frame of 1544Kbits/s. In this case, it corresponds to the Extra bit (193th). 24 CLOCK Master Clock input pin. Typ. operating Frequencies are: 3.072MHz for 24 PCM channels frame (192 bit/frame) 3.088MHz for 24 PCM channels frame with extra bit (193 bit/frame) 4.096MHz for 32 PCM channels frame (256 bit/frame) 8.192MHz for 64 PCM channels frame (512 bit/frame) Both M34116 an M116 operating modes are possible up to 4.096MHz. At 8.192MHz only M34116 operating mode is possible. 25 EC External Clock output pin. This pin provides the master clock for the Digital Switching Matrix (M3488). Normally it is the same signal as applied to the CLOCK input (pin 20). When the Extra bit is selected with the instruction 5, the first two periods of the master clock are canceled in order to allow the operation of the M34116 and the DSM with PCM frame with Extra bit (e.g. 193 bit/frame with PCM I/O of 1544Kbits/s). 27 IN PCM PCM input pin. The max bit rate is 4096Kbits/s. The first bit of the first cahnnel is found at the second rising edge of the CLOCK signal following the rising edge of the SYNC signal. If Extra bit is selected, then the first bit is shifted by two CLOCK periods. 28 A/MU A Law or MU Law select pin. When A/MU = 1, A Law is selected. When A/MU = 0, MU Law is selected. The law selection must be done before initializing the device using the RESET pin. 1 Vss Ground. 3/23
M34116
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Vi VO CLOCK Freq. SYNC Freq. Top Supply Voltage Input Voltage Off State Output Voltage Input Clock Frequency Input Synchronization Frequency Operating Temperature Parameter Value 4.75 to 5.25 0 to 5.25 0 to 5.25 3.072/3.088 4.096 / 8.192 (*) 8 0 to 70 Unit V V V MHz MHz KHz C
CAPACITANCES (measurements frequency = 1MHz; 0 to 70C; unused pins tied to VSS)
Symbol CI CI/O CO Parameter Input Capacitance I/O Capacitance Output Capacitance 6 to 13 4, 5, 21 Pin (**) 1 to 3; 15 to 20; 22 to 23 Min. Typ. Max. 5 15 10 Unit pF pF pF
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All DC characteristic are valid 250s after VCC and clock have been applied.
Symbol VIL Parameter Input Low Level Pins (**) 1 to 3 15 to 20 22 to 23 1 to 3 15 to 20 22 to 23 6 to 13 (***) 6 to 13 (***) 6 to 13 (***) 4,6 to 13,21 4 to 13, 21 5 1 to 3 6 to 13 15 to 20 22 to 23 6 to 13 14 VCC = 5V VCC = 5V VCC = 5V IOL = 2mA IOH = 1mA IOL = 4.1mA VIN = 0 to VCC VCC-0.4 0.4 10 Test Condition Min. - 0.3 Typ. Max. +0.8 Unit V
VIH
Input High Level
2.0
VCC
V
VT- VT+ VHY VOL VOH VOL IIL
Negative Threshold Voltage Positive Threshold Voltage Hysteresis Output Low Level Output High Level Output Low Level Input Leakage Current
0.6 1.5 0.4
0.9 1.7 0.8
1.1 2
V V V
0.4
V V V A
IOL ICC
Data Bus Leakage Current Supply Current
VIN = 0 to VCC CS = VCC Clock Freq. = 4.096MHz
10 50
A mA
(*) Only in M34116 Operating Mode. (**) Pin numbers referred to the DIP24. (***) Schimitt-trigger inputs.
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M34116
ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VCC = 5V 5%) All DC characteristic are valid 250s after VCC and clock have been applied. CL is the max. capacitive load and RL the test pull up resistor.
Signal CK Up to 4.096MHz Symbol tCK tWL tWH tR tF tCK tWL tWH tR tF tSL tHL tSH tWH tS tH tPD min. tPD max. tSL tHL tSH tWH tWL tWH tREP tSH tHH tR tF RD tWL tWH tREP tSH tHH tR tF
Notes: 1. With Extra Bit operating mode insert this time becomes 3 tCK. 2. With Extra Bit operating mode insert these times are 80ns longer. 3. With OPCODE (C/D = I), this time becomes 4tck (6tck if E = 1). E: extra bit indication in "operating mode" instruction. 4. For tone generation instruction, this time becomes 4tck (6tck if E = 1) E: extra bit indication in "operating mode" instruction. 5. With extra bit operating mode insert, this time becomes 6tck. 6. The initialization routine takes 2 frames time starting from the rising edge of RESET - Any access to the device should take place after the initialization routine is completed. (2 frames time).
Parameter Clock Period Clock Low Level Width Clock High Level Width Rise Time Fall Time Clock Period Clock Low Level Width Clock High Level Width Rise Time Fall Time Low Level Set-up Time Low Level Hold Time High Level Set-up Time High Level Width Set-up Time Hold Time Propagation Time Low Level referred to CK Propagation Time High level Referred to CK Low Level Set-up Time Low Level Hold Time High Level Set-up Time High Level Width Low Level Width High Level Width Repetition interval between active pulses. High Level st-up time to active read strobe. High Level hold time to active read strobe. Rise Time Fall Time Low Level Width High Level Width Repetition interval between active pulses. High Level st-up time to active read strobe. High Level hold time to active read strobe. Rise Time Fall Time
Test Condition
Min. 230 100 100
Typ.
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
25 25 120 50 50 10 10 See note 1 30 30 30 tCK 35 35 CL = 50pF RL = 1K 40 180 note 6 50 30 30 tCK 150 200 500 0 20 60 60 180 200 4 tCK 0 20 60 60
CK 8.192MHz
SYNC
PCM Input PCM Output (Open drain) RESET
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
WR
note 3 and 4
note 5
5/23
M34116
ELECTRICAL CHARACTERISTICS (continued)
Signal
CS
Symbol tSL (CS-WR) tHL (CS-WR) tSH (CS-WR) tHH (CS-WR) tSL (CS-RD) tHL (CS-RD) tSH (CS-RD) tHH (CS-RD)
Parameter Low level set-up time to WR falling edge. Low Level hold time from WR rising edge. High level set-up time to WR falling edge. High level hold time from WR rising edge. Low level set-up time to RD falling edge. Low Level hold time from RD rising edge. High level set-up time to RD falling edge. High level hold time from RD rising edge. Set-up time to write strobe end. Hold time from write strobe end. Set-up time to read strobe start. Hold time from read strobe end. Propagation time from rising edge of CK. Propagation time referred to CK edges. Set-up Hold Time Input set-up time to write strobe end. Input hold time from write strobe end. Propagation time from (active) falling edge of read strobe. Propagation time from (active) rising edge of read strobe to high impedance state.
Test Condition Active Case Active Case Inactive Case Inactive Case Active Case Active Case Inactive Case Inactive Case
Min. 0 20 0 20 0 0 0 0 130 25 20 25
Typ.
Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns
CD
tS(C/D-WR) tH(C/D-WR) tS(C/D-RD) tH(C/D-RD)
OS EC TD/TF D0 to D7 (interface bus)
tPD(OS) tPD(EC) tS tH tS(BUS-WR) tH(BUS-WR) tPD(BUS)
C L = 50pF C L = 50pF 80 40 130 25
100 30
ns ns ns ns ns ns
CL = 200pF
120
ns
tHZ(BUS)
80
ns
A.C. TESTING, OUTPUT WAVEFORM
A.C. testing inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0", timing measurement are made at 2.0V for a logic "1" and 0.8V for a logic "0".
6/23
M34116
Figure 2: Insertion Schema of M34116 in a 480 x 480 Non-Blocking Digital Switching Matrix
Figure 3: Block Diagram
EC RESET OS A/MU CS WR C/D RD
CLOCK DB(7:0) SYNC TIMING MPU INTERFACE
IN PCM
8 SR
PCM to LOG LIN 14
TONE CONTROL
19 FRAME RAM ADDER 19 CONF RAM
POWER 10 14
TONE ROM
LIN to PCM
SR OUT PCM
TF TD
D94TL130
7/23
M34116
CIRCUIT DESCRIPTION ALGORITHMS Conference. For each channel, the PCM signal coming in is added to its conference and the PCM signal of the previous frame is subtracted to its conference before being sent out. The output signal contains only the data of all the other channels in its conference except its own. Tone. A fourth of a sine wave equivalent to 3.9Hz (8KHz/2048) is stored in a ROM which is read at multiple of the step (modulus 512) equivalent to the specified frequency. This step is used until the duration is reached then a new step will be used according to the specified sequence. Attenuation gain. The PCM signal is converted to logarithmic of the equivalent linear and then added or subtracted to the specified level. It is then raised to the power of 10 to be converted back to linear. ARCHITECTURE The basic time slot (16 periods of the master clock) is divided in four different parts that perform four different operations (also refer to Fig. 2 block diagram): # input processing: attenuation or gain of input PCM according to the algorithm mentioned earlier. The serial PCM signal coming in is loaded as 8 bits parallel and converted to logarithmic of the linear (through the PCM to LOG LIN block). It is then added to the attenuation or gain levels (also in logarithmic) stored in the MPU interface, the result is raised to the power of 10 (through the POWER 10 block) to be converted back to linear and written in the FRAME RAM. # conference addition: the above PCM signal, amplified or attenuatedand converted in linear, is added to the conference and the result is stored in the conference RAM (block CONF RAM). # conference subtraction: the signal stored in the FRAME RAM during the previous frame is subtracted to the conference and the result is stored in the conference RAM. # output processing: attenuation or gain of the PCM to be sent out. The result of the above substraction is converted to PCM (through the block LIN to PCM) and to logarithmic (through the block PCM to LOG LIN), added to the attenuation or gain level stored in the MPU interface, converted to linear (through the block POWER 10) and then to PCM (through the block LIN to PCM). The resulting 8 bits are then shifted out serially. If a channel is in conference, then all the four above operations are applied. If it is in transparent mode, then only the first and last operations are applied. For tone generation, the two first operations are not used. During the third part, the tone ROM is read. Since the ROM data is in linear it can therefore be applied to the fourth operation for output processing. By default, after reset, the M34116 has the functionality and the instruction set of the M116. With a new operating mode instruction, the user can select the functionality of the M34116 with its new instruction set. The instruction set includes: operating mode: the user can choose either the M116 mode or the M34116 mode, the PCM byte format (no bit inverted, even bit inverted, odd bit inverted or all bit inverted) and the presence or not of the extra bit. conference connection: the user specifies which channel to be connected to which conference with the attenuationor gain levels to be applied to the PCM signal coming in and/or sent out. transparent connection: the user specifies which channel to be connected in transparent mode (bypass mode) with the attenuation or gain levels to be applied to the PCM signal coming in and/or sent out. tone generation: the user specifies to which channel the tone must be sent out with the attenuation or gain levels and the tone sequence. The sequence is composed of maximum 4 pairs of frequency-duration for tone and maximum 32 pairs of frequency-duration for melody. The frequency range is 3.9Hz to 3938Hz and the duration range is from 32ms to 8610ms. The user can specify either all of the pairs or finish the sequence with the byte hex FF. The M34116 will loop the specified sequence endlessly or until the channel is disconnected. The melody could be either a sine or square wave (pin programmable). channel disconnection: the user specifies which channel to be disconnected. A disconnected channel can be reconnected only after a minimum of one frame time. overflow status. The user specifies which of the 4 banks of 8 conferences to be monitored and the M34116 will send the status byte at the read operation. channel status. The user specifies the channel number and the M34116 will send out the status bytes at the read operation. These bytes include: conference number or transparent mode or tone or no connection, input attenuation or gain levels, output attenuation or gain levels. If the channel is in the tone mode, the tone sequence of frequency and duration will also be sent out.
8/23
M34116
INSTRUCTION SET OPERATING MODES Two different operating mode istructions are available: M116 Operating Mode: Sending this operating mode instruction, the device functionality is the same as M116 and M116 instruction set is selected (refer to the following M116 instruction set for further details).
Control Signal CS 0 RD 1 C/D 1 WR 0 D7 X D6 E D5 F1 Data Bus D4 F0 D3 0 D2 1 D1 0 D0 1
y E = 1 extra bit y F1- F0 = 00 no bit inverted 01 even bit inverted 10 odd bit inverted 11 all bit inverted
Default values after reset: E=0 F1- F0 = 11 if MU Law F1- F0 = 01 if A Law
M34116 Operating Mode: Sending this operating mode instruction, the M34116 instruction set and functionality are selected
Control Signal CS 0 RD 1 C/D 1 WR 0 D7 X D6 E D5 F1 Data Bus D4 F0 D3 1 D2 0 D1 0 D0 1
yE = 1 extra bit yF1- F0 = 00 no bit inverted 01 even bit inverted 10 odd bit inverted 11 all bit inverted
Note: Upon reset M116 instruction set is automatically selected. To switch from the M116 instruction set the above M34116 operating mode instruction is necessary. The operating mode instruction, when necessary, must be sent just after reset.
M34116 INSTRUCTION SET. INSTRUCTION 1: M34116 CHANNEL CONNECTION IN CONFERENCE MODE Five bytes are needed:
Control Signal CS 0 0 0 0 0 RD 1 1 1 1 1 C/D 0 0 0 0 1 WR 0 0 0 0 0 D7 X X X X X D6 X X X PT X D5 S X X C5 X Data Bus D4 P4 Al4 AO4 C4 X D3 P3 Al3 AO3 C3 0 D2 P2 Al2 AO2 C2 1 D1 P1 Al1 AO1 C1 1 D0 P0 Al0 AO0 C0 1
y S: Start bit y Al4-Al0: Al4 = 1 Al4 = 0 Al3-Al0 y Ol4-AO0: AO4 = 1 AO4 = 0 AO3-AO0 Input attenuationor gain (15dB) gain attenuation value in dB (0-15) output attenuationor gain (15dB) gain attenuation value in dB (0-15)
y PT: Phase toggle conference y P4-P0: Conference number (1-29) y C5-C0: Channel number (0-63) When S = 1 the conference register is cleared. S = 1 can be used only when connecting the first channel to a new conference. When PT = 1 the sign of the PCM samples is changed before they are put in conference. This corresponds to a phase shift of 180 and may be used to reduce the electrical echo. Note: Unspecified Data Bus can be either 0's or 1's
9/23
M34116
M34116 INSTRUCTION SET (continued) INSTRUCTION 2: M34116 CHANNEL CONNECTION IN TRANSPARENT MODE Four bytes are needed:
Control Signal CS 0 0 0 0 RD 1 1 1 1 C/D 0 0 0 1 WR 0 0 0 0 D7 X X X X D6 X X X X D5 X X C5 X Data Bus D4 Al4 AO4 C4 X D3 Al3 AO3 C3 0 D2 Al2 AO2 C2 0 D1 Al1 AO1 C1 1 D0 Al0 AO0 C0 1
y Al4-Al0: Al4 = 1 Al4 = 0 Al3-Al0
Input attenuationor gain (15dB) gain attenuation value in dB (0-15)
y AO4-AO0: output attenuation or gain (15dB) gain AO4 = 1 attenuation AO4 = 0 AO3-AO0 value in dB (0-15) y C5-C0: Channel number (0-63)
INSTRUCTION 3: M34116 CHANNEL DISCONNECTION This instruction is necessary to disconnect a party from a conference, to end a transparent mode connection or to end a tone generation. Two bytes are needed (same format as M116):
Control Signal CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 X X D6 X X D5 C5 X Data Bus D4 C4 X D3 C3 1 D2 C2 1 D1 C1 1 D0 C0 1
# C5-C0: Channel number (0-63) One time frame must exist between disconnection and connection of the same channel.
INSTRUCTION 4: M34116 OVERFLOW INFORMATION Single byte instruction:
Control Signal CS 0 RD 1 C/D 1 WR 0 D7 X D6 X D5 B1 Data Bus D4 B0 D3 1 D2 0 D1 1 D0 0
y B1-B0: Bank Selection (0-3) Conference overflow information is sent out, after this instruction, in the data bus (D7-D0) when RD goes low according to the Bank selection value:
Control Signal CS 0 0 0 0 RD 0 0 0 0 C/D 0 0 0 0 WR 1 1 1 1 Bank Selection B1 0 0 1 1 B0 0 1 0 1 D7 7 15 23 X D6 6 14 22 X D5 5 13 21 29 Conference Number D4 4 12 20 28 D3 3 11 19 27 D2 2 10 18 26 D1 1 9 17 25 D0 X 8 16 24
10/23
M34116
M34116 INSTRUCTION SET (continued) INSTRUCTION 5: M34116 TONE GENERATION Up to 7 Tone and 1 Melody channels may be active simultaneously. The instruction format for Tone and Melody is the same. For each Tone channel from 1 up to 4 couples of Step/Time may be specified while for the Melody channel from 1 up to 32 couples of Step/Time may be specified. Note: The Melody channel can be channel 0 or 8 or 16 or 24 etc. according to the following formula: Melody channel number = 0 + 8 x n (n = 0, 1, 2, 3, 4, 5, 6, 7) The Tone channel assignment follows the same rule: Tone 1 channel number = 1 + 8 x n (n = 0, 1, 2, 3, 4, 5, 6, 7) Tone 2 channel number = 2 + 8 x n (n = 0, 1, 2, 3, 4, 5, 6, 7) . .. .. ... ... . .. .. .. . .. . .. .. . .. ... ... ... ... .. .. Tone 7 channel number = 7 + 8 x n (n = 0, 1, 2, 3, 4, 5, 6, 7) This means that, selecting the tone 1 on the channel 9 (or and other one of its series), the channels 1, 17, 25.... can not be used for tones (or melody). The same is occuring for the tones 2...7 or the melody.
CS 0 0 0 0 0 0 0 : Control Signal RD C/D 1 0 1 0 1 1 1 0 1 0 1 0 1 0 : : WR 0 0 0 0 0 0 0 : D7 D6 D5 Data Bus D4 D3 AO4 AO3 C4 C3 1 S14 S13 T14 T13 S24 S23 T24 T23 : : D2 AO2 C2 1 S12 T12 S22 T22 : D1 AO1 C1 0 S11 T11 S21 T21 : D0 AO0 C0 0 S10 T10 S20 T20 :
S17 T17 S27 T27 :
S16 T16 S26 T26 :
S15 T15 S25 T25 :
optional end code:
0 1 0 0 1 1 1 1 1 1 1 1
opcode:
0 1 1 0 1 1 0 0
y AO4-AO0: Output attenuation or gain (15dB) AO4 = 1 gain, AO4 = 0 attenuation, AO3-AO0 value in dB (0-15) 0dB attenuation or gain correspond to -6dBm0 level. y C5-C0: Channel number (0-63) y Sn7-Sn0: Frequency Step for the n-th note in the tone sequence (n = 1-4 for tone n = 1-32 for melody). Step is a compressed coding of the frequency value. Given a frequency value f the value of S7-S0 can be calculated as follow: 32 1) calculate the linear step SL = round ( f x ) 125 2) apply the following table to get S7-S0 value from SL value (see also Appendix 1A and 1B).
S7 0 0 0 1 1 S6 0 0 1 0 1 0 0 0 0 1 0 0 0 1 S5 0 0 1 S5 S4 Linear Step SL 0 S5 1 S5 S5 S4 S4 S3 S3 S2 value (10 bit) S4 S3 S4 S3 S3 S2 S2 S1 S1 S0 S2 S2 S1 S0 0 S1 S1 S0 0 0 S0 S0 0 0 0 (SL decimal) (164) (*) (65->127) (**) (128->254) (256->508) (512->1008) STEP (Hz) 3.9 3.9 7.8 15.6 31.2
(*) For tone 7 only; (**) For melody and tone 1-6 Note: to obtain a Pause (Silence) -> S7-S0 must be all 0's y End code: if Less than 4 couples of Step/Time for tone or less than 32 for melody are to be specified then after the last couple of Step/Time a Step of all 1's (optional end code) must be sent before the opcode. Otherwise it must be skipped. y Tn7-Tn0: Specify the duration of the n'th note or pause. The time increment is 32ms. To get T7-T0 value, divide the wanted duration in ms by 32 and round to integer. Note: The minimum time between rising edges of successive WR for tone generation instruction is 4ck periods (6ck periods if EC = 1).
11/23
M34116
M34116 INSTRUCTION SET (continued) INSTRUCTION 6: M34116 STATUS The Status instruction can be used to read the contents of the instruction register and of the tone and melody registers. Two byte are needed:
Control Signal CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 D6 D5 C5 Data Bus D4 C4 D3 C3 0 D2 C2 1 D1 C1 1 D0 C0 0
y C5-C0: Channel number (0-63) After sending this instruction a variable number of Read can be sent depending on the type of operation that performs the channel (conference, transparent, tone, or melody). The first 3 Read, common to all type of operation, will send on the Data Bus the following data relative to the channel (C5-C0):
Control Signal CS 0 0 0 RD 0 0 0 C/D 0 0 0 WR 1 1 1 D7 IT D6 PT D5 Data Bus D4 P4 AI4 AO4 D3 P3 AI3 AO3 D2 P2 AI2 AO2 D1 P1 AI1 AO1 D0 P0 AI0 AO0
Note: P4-P0 = 0 means that the channel is disconnected so any following data read is meaningless. P4-P0 = 1 to 29 is the conference number. P4-P0 = 30 means that the channel operation is Tone or Melody. P4-P0 = 31 means that the channel operation is transparent connection. If the channel operation is Tone or Melody (P4 - P0 = 30) then the subsequent Read will send on the Data Bus the couples of Step/Time:
Control Signal CS 0 0 0 0 : RD 0 0 0 0 : C/D 0 0 0 0 : WR 1 1 1 1 : D7 S17 T17 S27 T27 : D6 S16 T16 S26 T26 : D5 S15 T15 S25 T25 : Data Bus D4 S14 T14 S24 T24 : D3 S13 T13 S23 T23 : D2 S12 T12 S22 T22 : D1 S11 T11 S21 T21 : D0 S10 T10 S20 T20 :
Notes: -Tone and Melody status reading ends if an all 1's Step value is found, otherwise the reading is cyclic. -The minimum time from the rising edge of the WR (with opcode) to the falling edge of first RD is 4clock periods (6clock periods if E = 1) unless the selected channel has been disconnected. In this case, one time frame must exist between the disconnect command and the read status command. The RD period is minimum 4clock periods (6clock periods if E = 1). - for both modes (M34116 and M116) the minimum time between two successive rising edges of the WR with opcode (C/D = 1) is 4clock periods (6clock periods if E = 1). E: Extra bit indication in "Operating mode" instruction.
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M34116
M116 INSTRUCTION SET INSTRUCTION 1: CHANNEL CONNECTION IN CONFERENCE MODE Three byte are needed: 1)The first byte contains the conference number (bits D0-D3) and the Start bit S (bit D4). When S = 1, all registers of the conference will be cleared. S = 1 is only required in the instruction 1 set of the first channel connected to a new conference. 2)The second byte contains in the bits (D0-D4) the number of the channel to be connected and the Insert Tone Enable bit IT (D5). When bit IT = 1 all the channels belonging to that conference are enabled using insert tone function if it's active (TD = 1). 3) The third byte contains information about the attenuationlevel to be applied to that channel and the opcode (0111). Instruction 1 Format
Control Signal CS 0 0 0 RD 1 1 1 C/D 0 0 1 WR 0 0 0 D7 X X A1 D6 X X A0 D5 X IT X Data Bus D4 S C4 X D3 P3 C3 0 D2 P2 C2 1 D1 P1 C1 1 D0 P0 C0 1
S: Conference Start bit P3-P0: Conference number (1-10) IT: Insertion Tone function enable (IT = 1) C4-C0: Channel number (0-31) A1-A0: Channel attenuation 00 = - 0dB 01 = - 3dB 10 = - 6dB INSTRUCTION 2: CHANNEL CONNECTION IN TRANSPARENT MODE Two bytes are needed: 1) The first byte contains the number of the channel. 2) The second byte contains information about the attenuation level to be applied to that channel and the opcode (0011). PCM data of this channel is not added to any conference and it is transferred to the PCM output. It is not affected by the tone control pins. Instruction 2 Format
Control Signal CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 X A1 D6 X A0 D5 X X Data Bus D4 C4 X D3 C3 0 D2 C2 0 D1 C1 1 D0 C0 1
INSTRUCTION 3: CHANNEL DISCONNECTION Two bytes are needed: 1) The first word contains the number of the channel to be disconnected. 2) The second word contains the opcode (1111). One time frame must exist between disconnection and connection of the same channel. Instruction 3 Format
Control Signal CS 0 0 RD 1 1 C/D 0 1 WR 0 0 D7 X X D6 X X D5 X X Data Bus D4 C4 X D3 C3 1 D2 C2 1 D1 C1 1 D0 C0 1
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M116 INSTRUCTION SET (continued) INSTRUCTION 4: OVERFLOW INFORMATION Two bytes are needed to know the status of all 10 conferences: C/D = 0 reads the first byte (first 8 conferences) and C/D = 1 reads the second byte (the last 2 conferences). A conference is in overflow when the corresponding bit is high. Instruction 4 Format
Control Signal CS 0 0 RD 0 0 C/D 0 1 WR 1 1 D7 CF8 X D6 CF7 X D5 CF6 X Data Bus D4 CF5 X D3 CF4 X D2 CF3 X D1 CF2 CF10 D0 CF1 CF9
CF10 - CF1: Conference in overflow when high. nb: as long as RD remains low, the overflow status of the conference selected by C/D can be monitored in real time. INSTRUCTION 5: OPERATING MODE The single byte needed contains the Extra bit (D6), the format bits F1-F0 (D5-D4) and the opcode (0101). The E bit must be E = 1 when the PCM frame contains a number of bit multiple of eight plus on bit (ex. PCM frame at 1544Kbit/s). Normally E = 0. The bits F1-F0 select the kinds of PCM format byte according table 1. After Reset the default values corresponds to F1 = 0, F0 = 1 if A-law is selected and F1 = 1, F0 = 1 if Mu-law is selected. All channels must be disconnected when the Operating Mode Instruction is sent. They must remain disconnected for at least two time frames after the instruction was sent. We recommende to use this instruction right after the RESET (see pin RESET decription). Instruction 5 Format
Control Signal CS 0 RD 1 C/D 1 WR 0 D7 X D6 E D5 F1 Data Bus D4 F0 D3 0 D2 1 D1 0 D0 1
E: Extra bit insertion (active when E = 1) F1 - F0: PCM byte Format selection (see also table 1) 00 = no bit inverted 01 = even bit (B0-B2-B4-B6) inverted 10 = odd bit (B1-B3-B5) inverted 11 = all bit (B0-B1-B2-B3-B4-B5-B6)inverted INSTRUCTION 6: STATUS Three bytes are needed: 1) The first byte contains the number of the channel; 2) The second byte contains the opcode (0110); 3) By a reding cycle you extract from the third byte the information about the operating mode of the channel (no connection or transparent mode or number of the conference, bits D4-D7); the attenuation (D2-D3) and noise suppression values (D0-D1) eventually inserted. This reading cycle must be executed at least one frame after the end of the opcode writing cycle. Instruction 6 Format
Control Signal CS 0 0 0 RD 1 1 0 C/D 0 1 1 WR 0 0 1 D7 X X P3 D6 X X P2 D5 X X P1 Data Bus D4 C4 X P0 D3 C3 0 A1 D2 C2 1 A0 D1 C1 1 T1 D0 C0 0 T0
P3-P0: channel mode operation information 0000 = no connection 1111 = transparent mode 1010 - 0001 = conference mode
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P3-P0 give the number of the conferenc nb: the instruction 6 enables the dat bus to read the status until reset by C/D = 0 and WR = 1.
M34116
Table 1 : PCM Byte Format. B7 (sign-bit) is the MSB and B0 is the LSB. F1-F0 corresponds to D5-D4 in the byte of the Operating Mode Instruction (instruction 5).
F1 0 F0 0 +FULL SCALE MIN LEVELS -FULL SCALE 0 0 +FULL SCALE MIN LEVELS -FULL SCALE 1 0 +FULL SCALE MIN LEVELS -FULL SCALE B7 1 1 0 0 1 1 0 0 1 1 0 0 B6 1 0 0 1 0 1 1 0 1 0 0 1 B5 1 0 0 1 1 0 0 1 0 1 1 0 B4 1 0 0 1 0 1 1 0 1 0 0 1 B3 1 0 0 1 1 0 0 1 0 1 1 0 B2 1 0 0 1 0 1 1 0 0 1 1 0 B1 1 0 0 1 1 0 0 1 0 1 1 0 B0 1 0 0 1 0 1 1 0 0 1 1 0
Figure 11: Overflow Control with P Interactive Procedure
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Figure 12: SYNC, PCM I/O, RESET, TD/TF Timings
(1) tbit corresponds to bit 0, channel 0 or Extra Bit.
Figure 13: WRITE Operating Timing.
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M34116
Figure 14: READ Operating Timing.
Figure 15: RC (External Clock) and OS (Overflow Signalling) Timings.
Figure 16: EC Timing with Extra Bit Operating Mode Insert.
Figure 17: OS Timing with Output PCM Channel n+1 belonging to a Conference in Overflow.
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M34116
APPENDIX 1A - Correspondancebetween S7-S0 values (HEX) and synthetized frequency for melody and tone 1-6:
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M34116
APPENDIX 1B - Correspondence between S7-S0 values (HEX) and synthetized frequency for tone 7:
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M34116
APPENDIX 2 TONE GENERATION PROGRAMMING Example 1: f = 425Hz Duration 200ms ON, 200ms OFF, 600ms ON, 1000ms OFF Attenuation10dB Channel #0. Programming sequence:
Control Signal CS 0 0 0 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 1 1 1 C/D 0 0 1 0 0 0 0 0 0 0 0 1 WR 0 0 0 0 0 0 0 0 0 0 0 0 Data D7 . . . . D0 0AH 00H 0CH 2DH 06H 00H 06H 2DH 12H 00H 1FH 0CH
Example 2: f = 400Hz Duration: 375ms ON, 375ms OFF Attenuation5dB Channel #3 Programming sequence:
Control Signal CS 0 0 0 0 0 0 0 0 0 RD 1 1 1 1 1 1 1 1 1 C/D 0 0 1 0 0 0 0 0 1 WR 0 0 0 0 0 0 0 0 0 Data D7 . . . . D0 05H 03H 0CH 26H 0CH 00H 0CH FFH 0CH
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M34116
PLCC28 PACKAGE MECHANICAL DATA
DIM. MIN. A B D D1 D2 E e e3 F F1 G M M1 1.24 1.143 12.32 11.43 4.2 2.29 0.51 9.91 1.27 7.62 0.46 0.71 0.101 0.049 0.045 10.92 mm TYP. MAX. 12.57 11.58 4.57 3.04 MIN. 0.485 0.450 0.165 0.090 0.020 0.390 0.050 0.300 0.018 0.028 0.004 0.430 inch TYP. MAX. 0.495 0.456 0.180 0.120
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M34116
DIP24 PACKAGE MECHANICAL DATA
DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 27.94 14.1 0.175 0.130 0.23 1.27 32.2 16.68 0.598 0.100 1.100 0.555 mm TYP. 0.63 0.45 0.31 0.009 0.050 1.268 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
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M34116
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore Spain - Sweden - Switzerland - Taiwan - Thaliand - United Kingdom - U.S.A.
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